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DATA SHEET
MOS INTEGRATED CIRCUIT
MC-458CB642XS
8M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)
Description
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Features
Part number MC-458CB642XS-A75 MC-458CB642XS-A75L
The MC-458CB642XS is 8,388,608 words by 64 bits synchronous dynamic RAM module (Small Outline DIMM) on This module provide high density and large quantities of memory in a small space without utilizing the surfaceDecoupling capacitors are mounted on power supply line for noise reduction.
which 4 pieces of 128M SDRAM: PD45128163 are assembled. mounting technology on the printed circuit board.
* 8,388,608 words by 64 bits organization
* Clock frequency and access time from CLK
/CAS latency CL = 3 CL = 2 Clock frequency (MAX.) 133 MHz 100 MHz Access time from CLK (MAX.) 5.4 ns 6 ns 5.4 ns 6 ns
* Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge * Pulsed interface * Possible to assert random column address in every cycle * Programmable burst-length: 1, 2, 4, 8 and Full Page * Programmable /CAS latency (2, 3) * Automatic precharge and controlled precharge * CBR (Auto) refresh and self refresh * Single 3.3 V 0.3 V power supply * LVTTL compatible * 4,096 refresh cycles/64 ms * Burst termination by Burst Stop command and Precharge command * 144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm) * Unbuffered type * Serial PD
* Quad internal banks controlled by BA0, BA1 (Bank Select) * Programmable wrap sequence (Sequential / Interleave)
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information.
Document No. E0115N20 (Ver. 2.0) Date Published September 2001 (K) Printed in Japan
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This product became EOL in March, 2004.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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CL = 3 CL = 2
133 MHz 100 MHz
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MC-458CB642XS
Ordering Information
Part number Clock frequency MHz (MAX.) MC-458CB642XS-A75 133 MHz 144-pin Small Outline DIMM (Socket Type) MC-458CB642XS-A75L 133 MHz Edge connector: Gold plated 25.4 mm height 4 pieces of PD45128163G5 (Rev. X) (10.16 mm (400) TSOP (II)) Package Mounted devices
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Data Sheet E0115N20
MC-458CB642XS
Pin Configuration
144-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
Vss DQ 32 DQ 33 DQ 34 DQ 35 Vcc DQ 36 DQ 37 DQ 38 DQ 39 Vss DQMB4 DQMB5 Vcc A3 A4 A5 Vss DQ 40 DQ 41 DQ 42 DQ 43 Vcc DQ 44 DQ 45 DQ 46 DQ 47 Vss NC NC
Vss DQ 0 DQ 1 DQ 2 DQ 3 VCC DQ 4 DQ 5 DQ 6 DQ 7 Vss DQMB0 DQMB1 VCC A0 A1 A2 Vss DQ 8 DQ 9 DQ 10 DQ 11 VCC DQ 12 DQ 13 DQ 14 DQ 15 Vss NC NC
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
/xxx indicates active low signal.
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62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
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CLK0 CKE0 Vcc Vcc /RAS /CAS /WE NC /CS0 NC NC NC NC CLK1 Vss Vss NC NC NC NC VCC Vcc DQ 16 DQ 48 DQ 17 DQ 49 DQ 18 DQ 50 DQ 19 DQ 51 Vss Vss DQ 20 DQ 52 DQ 21 DQ 53 DQ 22 DQ 54 DQ 23 DQ 55 Vcc Vcc A6 A7 A8 BA0 (A13) Vss Vss A9 BA1 (A12) A10 A11 Vcc Vcc DQMB2 DQMB6 DQMB3 DQMB7 Vss Vss DQ 24 DQ 56 DQ 25 DQ 57 DQ 26 DQ 58 DQ 27 DQ 59 VCC Vcc DQ 28 DQ 60 DQ 29 DQ 61 DQ 30 DQ 62 DQ 31 DQ 63 Vss Vss SDA SCL VCC Vcc
61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143
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Data Sheet E0115N20
A0 - A11
: Address Inputs
[Row: A0 - A11, Column: A0 - A8] BA0 (A13), BA1 (A12) : SDRAM Bank Select DQ0 - DQ63 CLK0, CLK1 CKE0 /CS0 : Data Inputs/Outputs : Clock Input : Clock Enable Input : Chip Select Input : Row Address Strobe : Column Address Strobe : Write Enable : DQ Mask Enable : Serial Data I/O for PD : Clock Input for PD
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/RAS /CAS /WE DQMB0 - DQMB7 SDA SCL VCC VSS NC
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: Power Supply : Ground : No Connection 3
MC-458CB642XS
Block Diagram
/WE /CS0 DQMB0 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 LDQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 UDQM DQ 15 DQ 14 DQ 13 DQ 12 DQ 11 DQ 10 DQ 9 DQ 8 D0
/CS /WE
DQMB4 DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39 DQMB5 DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47
LDQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 UDQM DQ 15 DQ 14 DQ 13 DQ 12 DQ 11 DQ 10 DQ 9 DQ 8
/CS
/WE
D2
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DQMB1 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 DQMB2 DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23 DQMB3 DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31 SCL A0 - A11 BA0 BA1
Remarks 1. D0 - D3: PD45128163 (2M words x 16 bits x 4 banks) 2. The value of all resistors is 10 .
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LDQM
/CS
/WE
DQ 7 DQ 6 DQ 5 DQ 4 DQ 3 DQ 2 DQ 1 DQ 0
DQMB6 DQ 48 DQ 49 DQ 50 DQ 51 DQ 52
LDQM DQ 7 DQ 6 DQ 5 DQ 4 DQ 3 DQ 2 DQ 1 DQ 0 UDQM DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15
/CS
/WE
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D1 SDA A1 A2 CLK0 A0 - A11 : D0 - D3 A13 : D0 - D3 A12 : D0 - D3
DQ 53 DQ 54 DQ 55
D3
UDQM DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15
DQMB7 DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62
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DQ 63 VCC C VSS CLK : D0 - D3 /RAS /CAS CKE0
SERIAL PD
D0 - D3 D0 - D3
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10 CLK1 10 pF /RAS : D0 - D3 /CAS : D0 - D3 CKE : D0 - D3
A0
4
Data Sheet E0115N20
MC-458CB642XS
Electrical Specifications
* All voltages are referenced to VSS (GND). * After power up, wait more than 100 s and then, execute power on sequence and CBR (Auto) refresh before proper device operation is achieved.
Absolute Maximum Ratings
Parameter Voltage on power supply pin relative to GND Voltage on input pin relative to GND Short circuit output current Symbol VCC VT IO PD TA Tstg Condition Rating -0.5 to +4.6 -0.5 to +4.6 50 4 0 to 70 -55 to +125 Unit V V mA W C C
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Power dissipation Storage temperature
Operating ambient temperature
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Supply voltage High level input voltage Low level input voltage Operating ambient temperature
Capacitance (TA = 25 C, f = 1 MHz)
Parameter Input capacitance
Data input/output capacitance
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Symbol VCC
Condition
MIN. 3.0 2.0 -0.3 0
TYP. 3.3
MAX. 3.6 VCC + 0.3 +0.8 70
Unit V V V C
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VIH VIL TA Symbol CI1 Test condition A0 - A11, BA0 (A13), BA1 (A12), /RAS, /CAS, /WE CI2 CI3 CI4 CI5 CI/O CLK0 CKE0 /CS0 DQMB0 - DQMB7 DQ0 - DQ63
Data Sheet E0115N20
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MIN. 15 23 15 15 5 5
TYP.
MAX. 30
Unit pF
37 26 26
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10 12 pF
5
MC-458CB642XS
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter Operating current Symbol ICC1 Test condition Burst length = 1, tRC tRC (MIN.) /CAS latency = 2 /CAS latency = 3 Precharge standby current in power down mode Precharge standby current in non power down mode ICC2NS Active standby current in power down mode ICC3P ICC3PS ICC3N ICC2P ICC2PS ICC2N CKE VIL (MAX.), tCK = 15 ns CKE VIL (MAX.), tCK = CKE VIH (MIN.), tCK = 15 ns, /CS VIH (MIN.), Input signals are changed one time during 30 ns. CKE VIH (MIN.), tCK = , Input signals are stable. CKE VIL (MAX.), tCK = 15 ns CKE VIL (MAX.), tCK = CKE VIH (MIN.), tCK = 15 ns, /CS VIH (MIN.), Input signals are changed one time during 30 ns. ICC3NS ICC4 CKE VIH (MIN.), tCK = , Input signals are stable. tCK tCK (MIN.), IO = 0 mA /CAS latency = 2 /CAS latency = 3 ICC5 tRC tRC (MIN.) /CAS latency = 2 /CAS latency = 3 -** -**L Input leakage current Output leakage current High level output voltage Low level output voltage II(L) VI = 0 to 3.6 V, All other pins not under test = 0 V -4 -1.5 2.4 0.4 80 580 740 920 960 8 3.2 +4 +1.5 mA mA mA 3 mA 2 32 20 16 120 mA mA MIN. MAX. 440 460 4 4 80 mA mA Unit mA Notes 1
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Active standby current in non power down mode Operating current (Burst mode) CBR (Auto) refresh current Self refresh current
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
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ICC6 IO(L) VOH VOL
CKE 0.2 V
A A
V V
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DOUT is disabled, VO = 0 to 3.6 V IO = -4.0 mA IO = +4.0 mA
Data Sheet E0115N20
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MC-458CB642XS
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions
Parameter AC high level input voltage / low level input voltage Input timing measurement reference level Transition time (Input rise and fall time) Output timing measurement reference level Value 2.4 / 0.4 1.4 1 1.4 Unit V V ns V
tCK tCH CLK 2.4 V 1.4 V 0.4 V tSETUP tHOLD 2.4 V 1.4 V 0.4 V tAC tOH tCL
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Input
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Output
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Data Sheet E0115N20
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MC-458CB642XS
Synchronous Characteristics
Parameter Symbol MIN. Clock cycle time /CAS latency = 3 /CAS latency = 2 Access time from CLK /CAS latency = 3 /CAS latency = 2 CLK high level width CLK low level width Data-out hold time /CAS latency = 3 /CAS latency = 2 tCK3 tCK2 tAC3 tAC2 tCH tCL tOH3 tOH2 tLZ /CAS latency = 3 /CAS latency = 2 tHZ3 tHZ2 tDS tDH tAS tAH tCKS tCKH tCKSP tCMS 2.5 2.5 3 3 0 3 3 1.5 0.8 1.5 0.8 1.5 0.8 1.5 5.4 6 7.5 10 -A75 MAX. (133 MHz) (100 MHz) 5.4 6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 Unit Note
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Data-out low-impedance time Data-in setup time Data-in hold time Address setup time Address hold time CKE setup time CKE hold time DQMB0 - DQMB7) hold time
Data-out high-impedance time
CKE setup time (Power down exit) Command (/CS0, /RAS, /CAS, /WE, DQMB0 - DQMB7) setup time Command (/CS0, /RAS, /CAS, /WE,
Note 1. Output load
Remark These specifications are applied to the monolithic device.
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Output
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1.5 tCMH 0.8
Z = 50 50 pF
Data Sheet E0115N20
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MC-458CB642XS
Asynchronous Characteristics
Parameter Symbol MIN. ACT to REF/ACT command period (Operation) REF to REF/ACT command period (Refresh) ACT to PRE command period PRE to ACT command period Delay time ACT to READ/WRITE command ACT (one) to ACT (another) command period Data-in to PRE command period /CAS latency = 3 /CAS latency = 2 tRC tRC1 tRAS tRP tRCD tRRD tDPL3 tDPL2 tDAL3 tDAL2 tRSC tT tREF 67.5 67.5 45 20 20 15 8 8 1CLK+22.5 1CLK+20 2 0.5 30 64 120,000 -A75 MAX. ns ns ns ns ns ns ns ns ns ns CLK ns ms 1 Unit Note
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period (Auto precharge) Mode register set cycle time Transition time
Data-in to ACT (REF) command /CAS latency = 3 /CAS latency = 2
Refresh time (4,096 refresh cycles)
Note 1. This device can satisfy the tDAL3 spec of 1CLK+20 ns for up to and including 125 MHz operation.
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Data Sheet E0115N20
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MC-458CB642XS
Serial PD
Byte No. 0 Function Described Defines the number of bytes written into serial PD memory 1 2 3 4 5 6 7 8 9 Total number of bytes of serial PD memory Fundamental memory type Number of rows Number of columns Number of banks Data width 08H 04H 0CH 09H 01H 40H 00H 01H -A75 -A75 75H 54H 00H 80H 10H 00H 01H 8FH 04H 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1 0 20 ns 15 ns 20 ns 10 ns 6 ns 256 bytes SDRAM 12 rows 9 columns 1 bank 64 bits 0 LVTTL 7.5 ns 5.4 ns None Normal x16 None 1 clock 1, 2, 4, 8, F 4 banks 2, 3 0 0 Hex 80H Bit 7 1 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
(1/2)
Notes 128 bytes
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Voltage interface CL = 3 Cycle time 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25-26 27 28 29 30 31 tRP (MIN.) tRRD (MIN.) tRCD (MIN.) tRAS (MIN.) Refresh rate/type SDRAM width CL = 2 Cycle time
Data width (continued)
CL = 3 Access time
DIMM configuration type
Error checking SDRAM width Minimum clock delay
Burst length supported Number of banks on each SDRAM /CAS latency supported /CS latency supported /WE latency supported SDRAM module attributes
SDRAM device attributes: General
CL = 2 Access time
Module bank density
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-A75 -A75 -A75 -A75 -A75 -A75
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06H 0 0 0 01H 0 0 0 01H 0 0 0 00H 0 0 0 0EH 0 0 0 A0H 60H 00H 14H 0FH 14H 2DH 10H 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Data Sheet E0115N20
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0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 1 0 1 0 1 1 1 0 0
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0 0 45 ns 0 0 64M bytes
10
MC-458CB642XS
(2/2)
Byte No. 32 Function Described Command and address signal setup time 33 Command and address signal hold time 34 35 36-61 62 SPD revision -A75 -A75 Data signal input setup time Data signal input hold time -A75 -A75 15H 08H 00H 12H A6H 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 1.2 A 1.5 ns 0.8 ns -A75 08H 0 0 0 0 1 0 0 0 0.8 ns -A75 Hex 15H Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 1 Bit 3 0 Bit 2 1 Bit 1 0 Bit 0 1 Notes 1.5 ns
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63 64-71 72 73-90 91-92 Revision code 93-94 95-98 99-125 126 127 Mfg specific latency support
Checksum for bytes 0 - 62
Manufacture's JEDEC ID code Manufacturing location
Manufacture's P/N
Manufacturing date Assembly serial number
Intel specification frequency Intel specification /CAS
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-A75
64H 87H
0 1
1 0
1 0
0 0
0 0
1 1
0 1
0 1
-A75
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Data Sheet E0115N20
Timing Chart
Refer to the PD45128441, 45128841, 45128163 Data sheet (E0031N).
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MC-458CB642XS
Package Drawing
144-PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B) M1 (AREA B) R Y N Q M L
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M2 (AREA A) I F
H C B
A
S
(OPTIONAL HOLES)
U1 T
U2
E D A1 (AREA A)
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12
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detail of A part W
ITEM A A1 B C D D1 D2 E F H I L M M1 M2 N Q R S T
MILLIMETERS 67.6 67.60.15 23.2 29.0 4.6 1.50.10 4.0 32.8 3.7 0.8 (T.P.) 3.3 20.0 25.40.15 3.4 22.0
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D2 X V
D1
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3.8 MAX. R2.0 4.00.10 1.8 1.00.1 U1 U2 V W X Y 3.2 MIN. 4.0 MIN. 0.25 MAX. 0.60.05 2.0 MIN. 2.55 MIN.
Data Sheet E0115N20
MC-458CB642XS
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0107
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
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2 3
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
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Data Sheet E0115N20
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CME0107
13
MC-458CB642XS
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
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M01E0107
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